1. Field of the Invention
This invention relates to the system architecture of a computer graphics display system. More particularly this invention relates to verifying the functions of a frame buffer employing a memory display interface.
2. Background
In a typical computer graphics system, a video random access memory (VRAM) frame buffer stores pixel data for a display device. A memory display interface provides pixel processing flexibility in such systems. The memory display interface is coupled to a digital to analog converter (DAC), which generates the video signals for the display device. The memory display interface processes pixel data at programmable pixel rates and pixel depths, and implements programmable pixel functions. Pixel processing at programmable pixel rates enables support of display devices having differing resolutions, and support of VRAM frame buffers having differing access speeds. Also, programmable pixel depths increases software compatibility.
A memory display interface processes pixel data through a set of pixel processing pipelines. The mapping of pixel data stored in the VRAM frame buffer to the pixel processing pipelines varies according to the pixel depth programmed into the memory display interface. The output pixel values generated by the memory display interface vary according to the pixel functions programmed into the memory display interface.
However, the programmable high speed pixel rates of the memory display interface create problems when verifying the VRAM frame buffer and the pixel processing function of the memory display interface. Usually, the processor bus in such system is not synchronized to the pixel busses. Also, a typical processor bus is to slow to read the high frequency data transferred over the pixel busses. Moreover, the multiple pixel processing pipelines within the memory display interface cannot easily be isolated by analyzing the pixel data transferred between the memory display interface and the DAC.
As will be described, the present test mode read back function enables a processor to verify the functions of a VRAM frame buffer and a memory display interface, wherein the memory display interface implements programmable pixel rates, pixel depths, and programmable pixel processing functions.